Recent computer-related technology has seen a dramatic improvement in signal processing speed. With this trend, the transmitting frequency of signals between circuit components such as LSIs has been increased to higher than ever before. When the transmitting frequency is raised, if signals are transmitted over the same distance as before, signal transmission loss increases to a non-negligible level. For example, in the wiring on a board in a computer used as a server, as the operating frequency increases, the transmission loss of high-frequency components, due to the skin effect, etc., increases to an appreciable level, and the sharpness of signal edges is lost, reducing the initial level of the signal at the receiver end.
The reduction of the signal level at the receiver end results in reduced resistance to signal noise and a reduced timing margin.
To compensate for such transmission loss, the prior art proposes a transmission technique such as disclosed in Japanese Unexamined Publication No. 2000-19681.
Japanese Unexamined Publication No. 2000-19681 describes a circuit in which the input signal is delayed by one cycle through a delay circuit, inverted by an inverter circuit and then added to the original input signal to emphasize the portion where signal data changes. However, this circuit has had the problem that the power consumption increases because a short circuit condition occurs when the input signal and its inverted signal are added together.